? semiconductor components industries, llc, 2001 october, 2001 rev. 15 1 publication order number: cs8182/d cs8182 micropower 200 ma low dropout tracking regulator/line driver the cs8182 is a monolithic integrated low dropout tracking regulator designed to provide adjustable buffered output voltage that closely tracks ( 10 mv) the reference input. the output delivers up to 200 ma while being able to be configured higher, lower or equal to the reference voltages. the output has been designed to operate over a wide range (2.8 v to 45 v) while still maintaining excellent dc characteristics. the cs8182 is protected from reverse battery, short circuit and thermal runaway conditions. the device also can withstand 45 v load dump transients and 50 v reverse polarity input voltage transients. this makes it suitable for use in automotive environments. the v ref /enable lead serves two purposes. it is used to provide the input voltage as a reference for the output and it also can be pulled low to place the device in sleep mode where it nominally draws less than 30 m a from the supply. features ? 200 ma source capability ? output tracks within 10 mv worst case ? low dropout (0.35 v typ. @ 200 ma) ? low quiescent current ? thermal shutdown ? short circuit protection ? wide operating range ? internally fused leads in so8 package current limit & sat sense + enable + esd esd esd thermal shutdown 2.0 v v out adj v ref /enable gnd v in figure 1. block diagram http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week pin connections and marking diagrams so8 df suffix case 751 d 2 pak 5pin dps suffix case 936a v in v out 8182 1 gnd gnd adj gnd gnd v ref /enable alyw device package shipping ordering information* cs8182ydf8 so8 95 units/rail cs8182ydfr8 so8 cs8182ydps5 d 2 pak 5pin 2500 tape & reel cs8182ydpsr5 * consult your local sales representative for so8 with exposed pads package option. d 2 pak 5pin 750 tape & reel 50 units/rail cs8182 awlyww 1 tab gnd pin 1. v in 2. v out 3. gnd 4. adj 5. v ref 1 5 1 8
cs8182 http://onsemi.com 2 maximum ratings* rating value unit storage temperature 65 to 150 c supply voltage range (continuous) 15 to 45 v supply voltage range (normal, continuous) 3.4 to 45 v peak transient voltage (v in = 14 v, load dump transient = 31 v) 45 v voltage range (adj, v out , v ref /enable) 10 to 45 v maximum junction temperature 150 c package thermal resistance, so8: junctiontocase, r q jc junctiontoambient, r q ja 45 165 c/w c/w package thermal resistance, d 2 pak, 5pin: junctiontocase, r q jc junctiontoambient, r q ja 4.0 1050** c/w c/w esd capability (human body model) 2.0 kv lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. **depending on thermal properties of substrate. r q ja = r q jc + r q ca
cs8182 http://onsemi.com 3 electrical characteristics (v in = 14 v; v ref /enable > 2.75 v; 40 c < t j < +125 c; c out 10 m f; 0.1 w < c outesr < 1.0 w @ 10 khz, unless otherwise specified.) parameter test conditions min typ max unit regular output v ref v out v out tracking error 4.5 v v in 26 v, 100 m a i out 200 ma, note 2 v in = 12 v, i out = 30 ma, v ref = 5.0 v, note 2 10 5.0 10 5 mv mv dropout voltage (v in v out ) i out = 100 m a i out = 30 ma i out = 200 ma 100 350 150 500 600 mv mv mv line regulation 4.5 v v in 26 v, note 2 10 mv load regulation 100 m a i out 200 ma, note 2 10 mv adj lead current loop in regulation 0.2 1.0 m a current limit v in = 14 v, v ref = 5.0 v, v out = 90% of v ref , note 2 225 700 ma quiescent current (i in i out ) v in = 12 v, i out = 200 ma v in = 12 v, i out = 100 m a v in = 12 v, v ref /enable = 0 v 15 75 30 25 150 55 ma m a m a reverse current v out = 5.0 v, v in = 0 v 0.2 1.5 ma ripple rejection f = 120 hz, i out = 200 ma, 4.5 v v in 26 v 60 db thermal shutdown gbd 150 180 210 c v ref /enable enable voltage 0.80 2.00 2.75 v input bias current v ref /enable 0.2 1.0 m a 2. v out connected to adj lead. package pin description package lead number so8 d 2 pak 5pin lead symbol function 8 1 v in input voltage. 1 2 v out regulated output. 2, 3, 6, 7 3 gnd ground. 4 4 adj adjust lead. 5 5 v ref /enable reference voltage and enable input.
cs8182 http://onsemi.com 4 circuit description enable function by pulling the v ref /enable lead below 2.0 v typically, (see figure 5 or figure 6), the ic is disabled and enters a sleep state where the device draws less than 55 m a from supply. when the v ref /enable lead is greater than 2.75 v, v out tracks the v ref /enable lead normally. output voltage the output is capable of supplying 200 ma to the load while configured as a similiar (figure 2), lower (figure 4), or higher (figure 3) voltage as the reference lead. the adj lead acts as the inverting terminal of the op amp and the v ref lead as the noninverting. the device can also be configured as a highside driver as displayed in figure 7. figure 2. tracking regulator at the same voltage v in v out gnd gnd v ref / gnd gnd adj enable loads 5.0 v b+ c1* 1.0 m f c2** 10 m f v out , 200 ma v out v ref figure 3. tracking regulator at higher voltages v in v out gnd gnd v ref / gnd gnd adj enable loads v ref b+ c1* 1.0 m f c2** 10 m f v out , 200 ma r a r f v out v ref (1 r e r a ) cs8182 cs8182 figure 4. tracking regulator at lower voltages v in v out gnd gnd v ref / gnd gnd adj enable loads v ref b+ c1* 1.0 m f c2** 10 m f v out , 200 ma v out v ref ( r2 r1 r2 ) r2 r1 figure 5. tracking regulator with enable circuit v in v out gnd gnd v ref / gnd gnd adj enable from mcu v ref b+ c1* 1.0 m f c2** 10 m f v out , 200 ma r cs8182 cs8182 figure 6. alternative enable circuit v in v out gnd gnd v ref / gnd gnd adj enable 10 m f figure 7. highside driver v in v out gnd gnd v ref / gnd gnd adj enable mcu b+ 200 ma v out b v sat ** c 2 is required for stability. * c 1 is required if the regulator is far from the power source filter. cs8182 cs8182 5.0 v i/o cs8101 6.0 v40 v v in 100 nf v ref (5.0 v) m c to load (e.g. sensor) c1* 1.0 m f
cs8182 http://onsemi.com 5 application notes switched application the cs8182 has been designed for use in systems where the reference voltage on the v ref /enable pin is continuously on. typically, the current into the v ref /enable pin will be less than 1.0 m a when the voltage on the v in pin (usually the ignition line) has been switched out (v in can be at high impedance or at ground.) reference figure 8. v out gnd gnd adj v in gnd gnd v ref / enable v out v ref 5.0 v v bat c1 1.0 m f ignition switch < 1.0 m a cs8182 figure 8. c2 10 m f external capacitors the output capacitor for the cs8182 is required for stability. without it, the regulator output will oscillate. actual size and type may vary depending upon the application load and temperature range. capacitor effective series resistance (esr) is also a factor in the ic stability. worstcase is determined at the minimum ambient temperature and maximum load expected. the output capacitor can be increased in size to any desired value above the minimum. one possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. the capacitor must also be rated at all ambient temperatures expected in the system. to maintain regulator stability down to 40 c, a capacitor rated at that temperature must be used. more information on capacitor selection for smart regulator ? s is available in the smart regulator application note, acompensation for linear regulators,o document number sr003an/d, available through the literature distribution center or via our website at http://www.onsemi.com. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 9) is: pd(max) { v in (max) v out (min) } i out (max) v in (max)i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current, for the application,and i q is the quiescent current the regulator consumes at i out(max) . once the value of pd(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heat sink will be required. figure 9. single output regulator with key performance parameters labeled i in i out i q smart v out v in regulator ? control features heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja: r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8182 http://onsemi.com 6 package dimensions so8 df suffix case 75106 issue t seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.19 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeter. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10 d 2 pak 5pin d suffix case 936a02 issue a 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t t optional chamfer
cs8182 http://onsemi.com 7 notes
cs8182 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8182/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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